1. Field
The following description relates to interrupt handling technology that may be used by a reconfigurable processor.
2. Description of the Related Art
A reconfigurable architecture is an architecture that can alter the hardware configuration is of a computing device based on the tasks to be performed by the computing device. When a task is processed using only hardware, it is difficult to efficiently handle even a slight alteration to the task due to the fixed hardware function. On the other hand, when a task is processed using only software, it is possible to alter the software according to the task and process the task using the altered software. However, the task is processed slower than when the task is processed using fixed hardware.
A reconfigurable architecture offers the advantages of both hardware and software. For these reasons, the use of reconfigurable architecture has increased, especially in the field of digital signal processing where the same tasks are often repeatedly performed.
There are a number of types of reconfigurable architecture, for example, a coarse-grained array (CGA). A CGA includes a plurality of processing units, and the connection state between the processing units may be changed according to each task to be performed.
However, problems arise when an interrupt occurs while a CGA is executing a loop operation. Examples of interrupts include a hardware interrupt, for example, an external input/output device, a timer, an exception such as an undefined instruction, and the like. Examples of interrupts also include software interrupts, for example, system calls, and the like. Generally, when an interrupt occurs, “context saving” is required. That is, current context stored in a register should be stored in a memory while the interrupt is handled and then should to be restored. However, because a CGA includes a plurality of register files, an excessive amount of overhead is created when an interrupt that occurs, because context from the plurality of registers is saved.